applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 S3005/s3006 evaluation board s6004 page 1 august 4, 1994 bicmos pecl clock generator evaluation board ? S3005/s3006 evaluation board s6004 vee vcc ledvcc refclkp dldp dldp refclkn tsdp rsdp tsdn llclkp rsdn llclkp llclkn lldp llclkn jp8 jp7 lldn s3 s1 reset s2 s3006 S3005 d1 u2 1 0 1 0 u1 S3005 xtal s3006 xtal gnd gnd ledgnd dldn dldn lldp lldn refclkn refclkp tsclkp tsclkn h1 h4 h2 jp10 jp9 ?v jp6 jp5 jp4 jp3 jp1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 h3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 jp2 jpb jpa figure 1. board layout evaluation board description the s6004 sonet evaluation board allows dem- onstration of amcc's S3005 and s3006 sonet/ sdh oc-3/12 transmitter/receiver chipset. this data sheet provides information on board contents and layout. it should be used in conjunction with the S3005/s3006 data sheets, which contain full techni- cal details on chip operation. figure 1 depicts the layout of the evaluation board, showing the location of connectors and components. power is supplied to the board from external sup- plies connected through the on-board banana jacks. connectors allow easy access to all of the interface signals on the S3005/s3006 chips.
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 page 2 s6004 S3005/s3006 evaluation board august 4, 1994 electrical connections the 60-pin header strips h1 and h3 allow simple ribbon cable connections to and from a user-pro- vided pattern generator. parallel data can be input to the S3005 transmitter either through the connector pins, or by using dip switch s1. the on-board led bank provides checks on output signals. dip switches s1, s2, and s3 allow access to the control signals of both the S3005 and s3006 chips. banana jacks are provided for the power connec- tions. coaxial sma connectors are used for serial data link and external reference clock connections. pin names pin no. level i/o description gnd 31 - - ground pclk 32 ttl/cmos o parallel clock gnd 33 - - ground gnd 34 - - ground gnd 35 - - ground lockdet 36 ttl o lock detect gnd 37 - - ground pin0 38 ttl i parallel data input gnd 39 - - ground pin1 40 ttl i parallel data input gnd 41 - - ground gnd 42 - - ground gnd 43 - - ground pin2 44 ttl i parallel data input gnd 45 - - ground pin3 46 ttl i parallel data input gnd 47 - - ground pin4 48 ttl i parallel data input gnd 49 - - ground pin5 50 ttl i parallel data input gnd 51 - - ground pin6 52 ttl i parallel data input gnd 53 - - ground pin7 54 ttl i parallel data input gnd 55 - - ground gnd 56 - - ground gnd 57 - - ground gnd 58 - - ground gnd 59 - - ground gnd 60 - - ground pin names pin no. level i/o description gnd 1 - - ground sync 2 ttl i synchronization enable gnd 3 - - ground refsel1 4 ttl i reference select 1 gnd 5 - - ground refsel0 6 ttl i reference select 0 gnd 7 - - ground mode2 8 ttl i mode select 2 gnd 9 - - ground mode1 10 ttl i mode select 1 gnd 11 - - ground mode0 12 ttl i mode select 0 gnd 13 - - ground dlcv 14 ttl i diag. line code violation gnd 15 - - ground dleb 16 ttl i diag. loopback enable gnd 17 - - ground lleb 18 ttl i line loopback enable gnd 19 - - ground table 2. h1 pin descriptions pae 20 ttl/cmos o phase alignment event gnd 21 - - ground rstb 22 ttl i master reset gnd 23 - - ground bytclkip 24 ttl/cmos o reference feedback clock gnd 25 - - ground testen 26 ttl i test clock enable gnd 27 - - ground piclk 28 ttl i parallel input clock gnd 29 - - ground gnd 30 C C ground refer to figure 1 for locations of the connectors dis- cussed in the following sections. all connectors, con- trols, and jumpers are labeled on the board. power connections power connections are made through the on-board banana jacks (vcc, vee, gnd, ledvcc, and ledgnd). refer to table 1 for recommended oper- ating conditions. a C2v connection provides proper on-board termination for the dldp/n outputs of the S3005 when connected to the dldp/n inputs of the s3006. table 1. power connection recommended operating conditions power supply nominal input voltage vcc 5 v ground 0 v vee -4.5 or -5.2v ledvcc 5 v
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 S3005/s3006 evaluation board s6004 page 3 august 4, 1994 pin names pin no. level i/o description sync 1 ttl input sync input (pin 58) of S3005 sync 2 ttl input dip switch s2 position 9 refsel1 3 ttl input refsel1 input (pin 28) of S3005 refsel1 4 ttl input dip switch s2 position 8 refsel0 5 ttl input refsel0 input (pin 27) of S3005 refsel0 6 ttl input dip switch s2 position 7 mode2 7 ttl input mode2 input (pin 66) of S3005 mode2 8 ttl input dip switch s2 position 6 mode1 9 ttl input mode1 input (pin 63) of S3005 and (pin 28) of s3006 mode1 10 ttl input dip switch s2 position 5 mode0 11 ttl input mode0 input (pin 65) of S3005 and (pin 29) of s3006 mode0 12 ttl input dip switch s2 position 4 dlcv 13 ttl input dlcv input (pin 59) of S3005 dlcv 14 ttl input dip switch s2 position 3 dleb 15 ttl input dleb input (pin 26) of S3005 and (pin 57) of s3006 dleb 16 ttl input dip switch s2 position 2 lleb 17 ttl input lleb input (pin 57) of S3005 lleb 18 ttl input dip switch s2 position 1 rstb 19 ttl input rstb input (pin 29) of S3005 and (pin 21) of s3006 rstb 20 ttl input reset switch testen 21 ttl input testen input (pin 31) of S3005 testen 22 ttl input dip switch s1 position 9 pin0 23 ttl input pin0 input (pin 14) of S3005 pin0 24 ttl input dip switch s1 position 8 pin1 25 ttl input pin1 input (pin 12) of S3005 pin1 26 ttl input dip switch s1 position 7 pin2 27 ttl input pin2 input (pin 10) of S3005 pin2 28 ttl input dip switch s1 position 6 pin3 29 ttl input pin3 input (pin 9) of S3005 pin3 30 ttl input dip switch s1 position 5 pin4 31 ttl input pin4 input (pin 8) of S3005 pin4 32 ttl input dip switch s1 position 4 pin5 33 ttl input pin5 input (pin 5) of S3005 pin5 34 ttl input dip switch s1 position 3 pin6 35 ttl input pin6 input (pin 3) of S3005 pin6 36 ttl input dip switch s1 position 2 pin7 37 ttl input pin7 input (pin 2) of S3005 pin7 38 ttl input dip switch s1 position 1 transmitter signalsheaders h1 and h2 header h1 allows connection to a 60-pin ribbon cable or to single discrete cables. controls for sig- nals rstb, dleb, mode0, and mode1 are com- mon to both transmitter and receiver and can be controlled via header h1. these signals can also be controlled by dipswitch s2 if h2 jumpers are installed. header h2 allows for dip switch control of signals sync, refsel [1:0], mode [2:0], dlcv, dleb, lleb, testen, and pin[7:0]. control of each sig- nal will be transferred to the corresponding dip switch si or s2 when the corresponding jumpers are installed on h2. (see table 3.) table 3. h2 pin descriptions
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 page 4 s6004 S3005/s3006 evaluation board august 4, 1994 receiver signalsheaders h3 and h4 header h3 allows connection to a 60-pin ribbon cable or to single discrete cables. (controls for sig- nals rstb, dleb, mode0, and mode1 are com- mon to both the transmitter and receiver and can be controlled via header h1. these signals can also be controlled by dipswitch s2 if h2 jumpers are in- stalled. mode2 is controlled via header h3. if the mode2 jumper is installed, the mode2 input will be low. if the mode2 jumper is not installed, the mode2 input will float to a high state.) when the associated pins on header h4 are jumpered, signals refsel [1:0] and testrst will be connected to dip switch s3. (see table 3.) without using any jumpers on these signal pins, they can be accessed directly by a 60-pin ribbon cable attached to header h3. signal pins pout [7:0] are always tied to led bank d1, and can also be accessed by the same 60- pin ribbon cable by jumpering those outputs on header h4. refer to table 4 for pin descriptions of header h3. pin names pin no. level i/o description gnd 31 - - ground poclk 32 ttl/cmos o parallel output clock gnd 33 - - ground gnd 34 - - ground gnd 35 - - ground testen 36 ttl i test clock enable gnd 37 - - ground refsel1 38 ttl i reference select 1 gnd 39 - - ground refsel0 40 ttl i reference select 0 gnd 41 - - ground gnd 42 - - ground gnd 43 - - ground testrst 44 ttl i test reset gnd 45 - - ground lcv 46 ttl/cmos o line code violation gnd 47 - - ground fp 48 ttl/cmos o frame pulse gnd 49 - - ground -50--- gnd 51 - - ground -52--- gnd 53 - - ground -54--- gnd 55 - - ground gnd 56 - - ground gnd 57 - - ground gnd 58 - - ground gnd 59 - - ground gnd 60 - - ground table 4. h3 pin description pin names pin no. level i/o description gnd 1 - - ground pout0 2 ttl/cmos o parallel data output gnd 3 - - ground pout1 4 ttl/cmos o parallel data output gnd 5 - - ground pout2 6 ttl/cmos o parallel data output gnd 7 - - ground pout3 8 ttl/cmos o parallel data output gnd 9 - - ground pout4 10 ttl/cmos o parallel data output gnd 11 - - ground pout5 12 ttl/cmos o parallel data output gnd 13 - - ground pout6 14 ttl/cmos o parallel data output gnd 15 - - ground pout7 16 ttl/cmos o parallel data output gnd 17 - - ground lockdet 18 ttl o lock detect gnd 19 - - ground oof 20 ttl i out of frame gnd 21 - - ground los 22 ecl i loss of signal gnd 23 - - ground mode2 24 ttl i operating mode gnd 25 - - ground -26--- gnd 27 - - ground bytclkip 28 ttl/cmos o ref. feedback clock gnd 29 - - ground gnd 30 - - ground reset when the rstb pins on header h2 are shorted to each other, the push button switch on the top left of the board is connected to the S3005 and s3006 rstb master reset inputs. crystal references and clock generation two 19.44-mhz differential ecl crystal oscillators with 100-ppm stability are provided, one each for the transmitter and receiver. if a higher reference fre- quency is needed (38.88, 51.84, or 77.76 mhz), it can be selected by setting the two reference select input pins. the correct frequency is set with the refsel[1:0] inputs as shown in table 6. the output clock frequency can be 155.52 mhz (sts-3), 311.04 mhz (sts-3 cmi), or 622.08 mhz (sts-12). the output frequency is set with the mode[2:0] inputs as shown in table 7.
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 S3005/s3006 evaluation board s6004 page 5 august 4, 1994 to use the S3005 crystal oscillator as its reference, install jumpers on jp8 and jp10. to use an external reference clock through the S3005 refclkp/n sma connector, install jumpers on jp7 and jp9. to use the s3006 crystal oscillator as its reference, in- stall jumpers on jp3 and jp5. to use an external reference clock through the s3006 refclkp/n sma connector, install jumpers on jp4 and jp6. (see table 9, jumpers.) leds the bank of 10 leds (d1) display when the S3005/ s3006 chips are locked, and also light when the ap- propriate pout is in the high state. the function of each led is shown in table 8, and is also labeled on the board. sma connectors sma connectors provide input/output capability for a number of signals, including serial data i/o and ref- erence clocks. these connectors are labeled on the board and are also shown in figure 1. table 5. h4 pin description pin names pin no. level i/o description pout0 1 ttl/cmos output pout0 output (pin 14) of s3006 pout0 2 ttl/cmos output connected to h3 pin 2 pout1 3 ttl/cmos output pout1 output (pin 12) of s3006 pout1 4 ttl/cmos output connected to h3 pin 4 pout2 5 ttl/cmos output pout2 output (pin 10) of s3006 pout2 6 ttl/cmos output connected to h3 pin 6 pout3 7 ttl/cmos output pout3 output (pin 9) of s3006 pout3 8 ttl/cmos output connected to h3 pin 8 pout4 9 ttl/cmos output pout4 output (pin 8) of s3006 pout4 10 ttl/cmos output connected to h3 pin 10 pout5 11 ttl/cmos output pout5 output (pin 5) of s3006 pout5 12 ttl/cmos output connected to h3 pin 12 pout6 13 ttl/cmos output pout6 output (pin 3) of s3006 pout6 14 ttl/cmos output connected to h3 pin 14 pout7 15 ttl/cmos output pout7 output (pin 2) of s3006 pout7 16 ttl/cmos output connected to h3 pin 16 refsel1 17 ttl input dip switch s3 position 1 refsel1 18 ttl input connected to h3 pin 38 refsel0 19 ttl input dip switch s3 position 2 refsel0 20 ttl input connected to h3 pin 40 testrst 21 ttl input dip switch s3 position 3 testrst 22 ttl input connected to h3 pin 44 jumpers a number of jumpers allow the user to control vari- ous aspects of the characterization procedure. the function of each jumper is described in table 9. refsel1 refsel0 frequency 0 0 19.44 mhz 0 1 38.88 mhz 1 0 51.84 mhz 1 1 77.76 mhz table 6. refsel settings freq. bypass mode normal mode (testen = 1) (testen = 0) mode2 mode1 mode0 mode2 mode1 mode0 622.08 mhz 1 0 0 1 0 0 311.04 mhz 1 0 1 0 0 1 155.52 mhz 1 1 0 0 1 0 table 7. output clock frequency settings
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 page 6 s6004 S3005/s3006 evaluation board august 4, 1994 bit error rate test procedure the following method is commonly used to run a serial bit error rate (ber) test on the s3006 device in sts-12 mode. this allows the use of a serial-out/serial-in bit error rate tester to verify the pll frequency/phase lock capabilities and jitter tolerance testing. 1. connect jumper wires between pout[7:0] (h3 pins 2, 4, 6, 8, 10, 12, 14, 16) on the s3006 and pin[7:0] (h1 pins 38, 40, 44, 46, 48, 50, 52, 54) on the S3005. 2. connect a jumper wire between poclk (h3 pin 32) on the s3006 and piclk (h1 pin 28) on the S3005. 3. connect the llclkp/n outputs of the s3006 to the refclkp/n inputs of the S3005 using sma cables. (be sure that jumpers jp7 and jp9 are connected and jumpers jp8 and jp10 are disconnected, as required when the S3005 refclkp/n sma connectors are used for an external reference.) 4. set testen (h1 pin 26) on the S3005 high, to put the S3005 into bypass mode, which bypasses the pll-generated clock source and enables the use of the refclkp/n as the bit rate clock input. (note that in bypass mode, the frequency of the refclk must be appropriate for the desired data rate. refer to the data sheet for more informa- tion.) mode [2, 1, 0] should be 1, 0, 0 on both the S3005 and s3006. at this point, serial data can be directed to the s3006, the parallel output data from the s3006 can be wrapped back to the parallel inputs of the S3005, and the serial outputs of the S3005 can be monitored. jp1 connects s3006 op-amp power supply to enable s3006 pll to function jp2 connects S3005 op-amp power supply to enable S3005 pll to function jp3, jp5 connects on-board xtal oscillator to s3006 refclk inputs jp4, jp6 connects refclkp/n smas to s3006 refclk inputs jp7, jp9 connects refclkp/n smas to S3005 refclk inputs jp8, jp10 connects on-board xtal oscillator to S3005 refclk inputs jpa, jpb connects S3005/s3006 lockdet outputs to led jumper function table 9. jumpers table 8. leds d1-a tx lockdet d1-b rx lockdet d1-c pout0 d1-d pout1 d1-e pout2 d1-f pout3 d1-g pout4 d1-h pout5 d1-i pout6 d1-j pout7 led function
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